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1. #SYNPLIFY PRO UTILIZE MORE PROCESSORS HOW TO#
2. #SYNPLIFY PRO UTILIZE MORE PROCESSORS SOFTWARE#
3. #SYNPLIFY PRO UTILIZE MORE PROCESSORS SERIES#

This saves not just time but also memory. The ODC step formalizes the process, so that when a constraint is applied to an object, that constraint loads only the relevant group. The GUI makes this process as easy and transparent as possible (Figure 2).įigure 3 Four steps to bring up a Distributed Synthesis job (Source: Synopsys) Alternatively, if a subproject is not ready when Tom wishes to attempt an initial synthesis, he can turn off that portion of the design and run the others. Where part of a subproject is still undergoing some editing, a ‘completed’ version of the work to date can be passed back to the top level while a separate file is still being edited in by the subproject holder. Similarly, Tom the architect can take projects back up to the main level for a synthesis or constraint check both during and at the end of the design. Fast Compile) and others that require reiterations that only cover an altered portion (e.g. Each subproject holder can use various tools that allow for incremental development using both express features (e.g. The advantages here go beyond the divisions. Subprojects can also be either ‘top-down’, passing the post-compile RTL netlist result (SRS) consisting of generic technology-independent primitives up to the top-level project or they can be ‘bottom-up’, passing the final post-map gate-level netlist (EDIF) consisting of technology specific primitives up to the top level project. Using HPM, Tom, the project architect, has created five ‘subprojects’ that comprise the target design, and assigned them to four engineers – Ivan owns one sub project that applies to two instances of the same module.Įach project can be worked on independently and in parallel and there is ample flexibility available when the architect decides where to set the boundaries, and what format they take.įor example, a subproject can be either instance- or module-based. Consider Figure 1:įigure 1 Hierarchical project management enables a divide and conquer strategy (Source: Synopsys) It is a ‘divide and conquer’ strategy enabled within Synplify, based on splitting up tasks into discrete blocks, or ‘subprojects’. HPM directly responds to combinatorial explosion. This is where more people – and by extension, more tasks – creates more communication channels and, for a design, more risk of a domino effect, in which a change to one part of the design ripples through others being undertaken by separate engineering teams. The first is ‘ramp-up’ time, the time it takes for new team members to become comfortable with the technology and challenges when they join a project. The management of any major design project needs to consider Brooks’ Law, which states that adding manpower to a project that is already late makes it later.įred Brooks said that delays will lengthen for two main reasons.

Hierarchical project management for FPGA synthesis

#SYNPLIFY PRO UTILIZE MORE PROCESSORS HOW TO#

HPM makes a useful starting point as it explains how to split up a design in process so that you can then apply to it the efficiencies available from, say, multi-processing.

#SYNPLIFY PRO UTILIZE MORE PROCESSORS SERIES#

Second, how – either within the main project or a series of subprojects – to exploit new tools and multi-processing, at the desktop or on a server farm.įor those who are focused on FPGA, we will look at some key technology features that have been added to and/or evolved within Synplify. First, how to divide and conquer complex projects to speed them on their way. This article discusses some of those features, in terms of their performance, and how they lift productivity in project management. But the way those numbers are achieved is, in some ways, as interesting and useful for planning projects as the results themselves.Ī number of features have been added to Synplify and others enhanced, each of which adds an incremental lift to productivity that is then consolidated in the whole.

#SYNPLIFY PRO UTILIZE MORE PROCESSORS SOFTWARE#

The headline figures for the latest release of the Synplify Pro and Synplify Premier FPGA synthesis software tools say that they can deliver up to 3X faster runtime and a 10% improvement in timing quality of results.

How parallelism in project management, synthesis and processing resources can accelerate FPGA-based design